Berkeley CS 61C Lecture 11

Here are some notes and corrections on this lecture:

Each note begins with a time; "ca." in front of a time means that it is approximate.

ca. 2:00 -- That should be 2S, not 2S on the slide.

37:00 ff -- There's a mux missing from the ALU. The book's datapath diagram is better than his.

55:20 -- By "ISA registers" on the slide, he means the registers that you can address with instructions: $0 ... $31. ISA is the Instruction-Set Architecture, so ISA registers are registers that are available to the instruction set. This is to distinguish them from other internal registers like the MAR, MBR, and CIR that you can't explicitly address.

58:30 -- The book has a different "MIPS-lite" subset but doesn't call it by that name.

1.07:00 ff. -- The book has a single "write" input for memory and registers; when it is pulsed, the write happens. The lecture uses a "write-enable" input and a clock input. Clock pulses come along regularly; a write will happen on any clock pulse when the write-enable signal is true. The book is a simplified version, but it's good enough for us. His version is more like the real thing.